1. Field of the Invention
The present invention relates to a programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type.
2. Discussion of the Related Art
In non-volatile memories it is particularly important to provide an architecture that allows quick programming of the memory with preset programming voltages.
In conventional architecture, the programming voltage of the various memory cells is never uniform due to the drops in voltage along the lines.
The case thus occurs in which the memory cells that are closer to the programming means are programmed with an optimum voltage, whereas, as one moves further away from the point where the programming voltage is generated, the programming voltage decreases due to the above mentioned voltage drops of the lines. Therefore, the memory cells which are more distant from the programming means are programmed with decreasing voltage values that can differ even considerably from those of the memory cells which are closer to the programming means.
In order to contain the non-uniformity of the programming voltage levels, it is necessary to program a small number of bits at a time, so that the voltage value differences are negligible.
This approach is valid when byte programming is performed. It is not equally valid when, during testing, parallel programming is performed to reduce programming time requirements.
Abandoning or containing parallel programming leads to the drawback of increasing the programming times at the detriment of the low cost of the finished memory device.
It is in fact evident that the programming of large memory matrices is hindered by the difficulty in achieving uniform programming voltages except for a small number of memory cells at a time.
This drawback will become increasingly important as memory construction technology improves, leading to ever larger sizes of memories. These larger sizes are achieved by reducing the thicknesses and the size of the programming lines (this entails higher resistivity).
Furthermore, in the case of the programming of multiple bits in parallel, using a redundancy system for output lines, if there are two defective cells in two different bit lines, it is not possible to resort to the redundancy lines provided for replacement of the defective lines, since it is not possible to apply redundancy to two different lines simultaneously. This results in the important drawback of having to reject, during testing, a memory device that has this situation, or of having to take a much longer time by using only byte programming.
Regarding the direct memory access function, this function is usually provided by virtue of additional lines that allow direct access to the memory for inspection purposes. The additional lines add to the normal lines provided for programming and reading the data, resulting in the drawback of increasing the space occupation of the memory device and of reducing its reliability.